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CY62157EV30 MoBL(R)
8 Mbit (512K x 16) Static RAM
Features

TSOP I Package Configurable as 512K x 16 or 1M x 8 SRAM High Speed: 45 ns Temperature Ranges Industrial: -40C to +85C Automotive-A: -40C to +85C Automotive-E: -40C to +125C Wide Voltage Range: 2.20V to 3.60V Pin Compatible with CY62157DV30 Ultra Low Standby Power Typical standby current: 2 A Maximum standby current: 8 A (Industrial) Ultra Low Active Power Typical active current: 1.8 mA at f = 1 MHz Easy Memory Expansion with CE1, CE2, and OE Features Automatic Power Down when Deselected CMOS for Optimum Speed and Power Available in Pb-free and non Pb-free 48-Ball VFBGA, Pb-free 44-Pin TSOP II and 48-Pin TSOP I Packages

advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE1HIGH or CE2 LOW), the outputs are disabled (OE HIGH), Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is active (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 10 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Functional Description
The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER
DATA IN DRIVERS
512K x 16/1M x 8 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
CE2 BYTE BHE WE OE BLE
A11 A12 A13 A14 A15 A16 A17 A18
Power Down Circuit
CE1 BHE BLE
CE2
CE1
Cypress Semiconductor Corporation Document #: 38-05445 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 26, 2009
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CY62157EV30 MoBL(R)
Pin Configuration
Figure 1. 48-Ball VFBGA (Top View) [2]
1 BLE IO8 IO9 VSS VCC IO14 IO15 A18 2 OE BHE IO10 IO11 IO12 IO13 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO1 IO3 IO4 IO5 WE A11 6 CE2 IO0 IO2 VCC VSS IO6 IO7 NC A B C D E F G H
Figure 2. 44-Pin TSOP II (Top View) [3]
A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 A8 A9 A10 A11 A12 A13
Figure 3. 48-Pin TSOP I (512K x 16/1M x 8) (Top View) [2, 4]
A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss IO15/A19 IO7 IO14 IO6 IO13 IO5 IO12 IO4 Vcc IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 OE Vss CE1 A0
Product Portfolio
Power Dissipation Product Range VCC Range (V) Min CY62157EV30LL Ind'l/Auto-A Auto-E 2.2 2.2 Typ [1] 3.0 3.0 Max 3.6 3.6 45 55 Speed (ns) Operating ICC, (mA) f = 1 MHz Typ [1] 1.8 1.8 Max 3 4 f = fmax Typ [1] 18 18 Max 25 35 Standby, ISB2 (A) Typ [1] 2 2 Max 8 30
Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 2. NC pins are not connected on the die. 3. The 44-TSOP II package has only one chip enable (CE) pin. 4. The BYTE pin in the 48-TSOP I package must be tied HIGH to use the device as a 512K x 16 SRAM. The 48-TSOP I package can also be used as a 1M x 8 SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).
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CY62157EV30 MoBL(R)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied .......................................... -55C to + 125C Supply Voltage to Ground Potential ............................... -0.3V to 3.9V (VCCmax + 0.3V) DC Voltage Applied to Outputs in High-Z State [5, 6] ............... -0.3V to 3.9V (VCCmax + 0.3V) DC Input Voltage [5, 6] ........... -0.3V to 3.9V (VCC max + 0.3V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... > 2001V (MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Device Range Ambient Temperature -40C to +125C VCC [7] 2.2V to 3.6V
CY62157EV30LL Ind'l/Auto-A -40C to +85C Auto-E
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70V IOL = 0.1 mA IOL = 2.1mA, VCC > 2.70V VCC = 2.2V to 2.7V VCC = 2.7V to 3.6V VCC = 2.2V to 2.7V VCC = 2.7V to 3.6V GND < VI < VCC 1.8 2.2 -0.3 -0.3 -1 -1 18 1.8 2 45 ns (Ind'l/Auto-A) Min 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 25 3 8 1.8 2.2 -0.3 -0.3 -4 -4 18 1.8 2 Typ
[1]
55 ns (Auto-E) Min 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +4 +4 35 4 30 Typ [1] Max
Max
Unit V V V V V V V V A A
VIL IIX IOZ ICC
Output Leakage GND < VO < VCC, Output Disabled Current VCC Operating Supply Current Automatic CE Power Down Current -- CMOS Inputs Automatic CE Power Down Current -- CMOS Inputs f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA f = 1 MHz CMOS levels CE1 > VCC - 0.2V, CE2 < 0.2V VIN > VCC - 0.2V, VIN < 0.2V) f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60V CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
mA A
ISB1
ISB2 [8]
2
8
2
30
A
Notes 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization. 8. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 9. Tested initially and after any design or process changes that may affect these parameters.
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CY62157EV30 MoBL(R)
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Test Conditions BGA 72 8.86 TSOP I 74.88 8.6 TSOP II 76.88 13.52 Unit C/W C/W Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, (Junction to Ambient) two-layer printed circuit board Thermal Resistance (Junction to Case)
Figure 4. AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE VCC 10% GND R2 Rise Time = 1 V/ns Equivalent to: ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
THEVENIN EQUIVALENT RTH OUTPUT V TH 3.0V 1103 1554 645 1.75 Unit V
Parameters R1 R2 RTH VTH
2.5V 16667 15385 8000 1.20
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CY62157EV30 MoBL(R)
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR
[8]
Description VCC for Data Retention Data Retention Current
Conditions
Min 1.5
Typ [1] Max Unit V 2 5 30 A
VCC= 1.5V, CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V
Ind'l/Auto-A Auto-E 0 tRC
[9]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
tR [10]
Data Retention Waveform
Figure 5. Data Retention Waveform [11]
DATA RETENTION MODE VCC CE1 or BHE.BLE or CE2
VCC(min) tCDR
VDR > 1.5V
VCC(min) tR
Notes 10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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CY62157EV30 MoBL(R)
Switching Characteristics
Over the Operating Range[12, 13] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[17] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z[14, 15] WE HIGH to Low-Z
[14]
Description
45 ns (Ind'l/Auto-A) Min 45 45 10 45 22 5 18 10 18 0 45 45 5 18 45 35 35 0 0 35 35 25 0 18 10 Max
55 ns (Auto-E) Min 55 55 10 55 25 5 20 10 20 0 55 55 10 20 55 40 40 0 0 40 40 25 0 20 10 Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to LOW-Z[14] High-Z[14, 15]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW and CE2 HIGH to Low-Z[14]
15]
CE1 HIGH and CE2 LOW to High-Z[14, CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to BLE/BHE HIGH to Low-Z[14, 16] HIGH-Z[14, 15]
Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4. 13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 16. If both byte enables are toggled together, this value is 10 ns. 17. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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CY62157EV30 MoBL(R)
Switching Waveforms
Figure 6 shows Address Transition Controlled read cycle waveforms.[18, 19] Figure 6. Read Cycle No. 1
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 7 shows OE Controlled read cycle waveforms. [19, 20] Figure 7. Read Cycle No. 2
ADDRESS tRC CE1 tPD CE2 tACE BHE/BLE tDBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC HIGH IMPEDANCE DATA VALID tHZBE tHZCE
Notes 18. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
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CY62157EV30 MoBL(R)
Switching Waveforms (continued)
Figure 8 shows WE Controlled write cycle waveforms.[17, 21, 22] Figure 8. Write Cycle No. 1
tWC ADDRESS tSCE CE1
CE2 tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 23 tHZOE VALID DATA
tHD
Figure 9 shows CE1 or CE2 Controlled write cycle waveforms.[17, 21, 22] Figure 9. Write Cycle No. 1
tWC ADDRESS tSCE CE1
CE2 tSA tAW tPWE tHA
WE
BHE/BLE
tBW
OE tSD DATA IO NOTE 23 tHZOE VALID DATA
tHD
Notes 21. Data I/O is high impedance if OE = VIH. 22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 23. During this period, the I/Os are in output state. Do not apply input signals.
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CY62157EV30 MoBL(R)
Switching Waveforms (continued)
Figure 10 shows WE Controlled, OE LOW write cycle waveforms.[22] Figure 10. Write Cycle No. 3
tWC ADDRESS tSCE CE1
CE2
BHE/BLE
tBW
tAW tSA WE tPWE
tHA
tSD DATA IO NOTE 23 VALID DATA
tHD
tHZWE Figure 11 shows BHE/BLE Controlled, OE LOW write cycle waveforms.[22] Figure 11. Write Cycle No. 4
tWC ADDRESS
tLZWE
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 23 VALID DATA tHD tBW tHA
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CY62157EV30 MoBL(R)
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High-Z High-Z High-Z Data Out (IO0-IO15) Data Out (IO0-IO7); High-Z (IO8-IO15) High-Z (IO0-IO7); Data Out (IO8-IO15) High-Z High-Z High-Z Data In (IO0-IO15) Data In (IO0-IO7); High-Z (IO8-IO15) High-Z (IO0-IO7); Data In (IO8-IO15) Mode Deselect/Power Down Deselect/Power Down Deselect/Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62157EV30LL-45BVI CY62157EV30LL-45BVXI CY62157EV30LL-45ZSXI CY62157EV30LL-45ZXI CY62157EV30LL-45BVXA CY62157EV30LL-45ZSXA CY62157EV30LL-45ZXA 55 CY62157EV30LL-55ZSXE CY62157EV30LL-55ZXE Package Diagram 51-85150 51-85150 51-85087 51-85183 51-85150 51-85087 51-85183 51-85087 51-85183 Package Type 48-ball Very Fine Pitch Ball Grid Array 48-ball Very Fine Pitch Ball Grid Array (Pb-free) 44-pin Thin Small Outline Package Type II (Pb-free) 48-pin Thin Small Outline Package Type I (Pb-free) 48-ball Very Fine Pitch Ball Grid Array (Pb-free) 44-pin Thin Small Outline Package Type II (Pb-free) 48-pin Thin Small Outline Package Type I (Pb-free) 44-pin Thin Small Outline Package Type II (Pb-free) 48-pin Thin Small Outline Package Type I (Pb-free) Automotive-E Automotive-A Operating Range Industrial
Contact your local Cypress sales representative for availability of these parts.
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CY62157EV30 MoBL(R)
Package Diagrams
Figure 12. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
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CY62157EV30 MoBL(R)
Package Diagrams (continued)
Figure 13. 44-Pin TSOP II, 51-85087
51-85087-*A
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CY62157EV30 MoBL(R)
Package Diagrams (continued)
Figure 14. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05]
1 N
0.020[0.50] TYP.
0.472[12.00]
0.007[0.17] 0.011[0.27]
0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE
0.002[0.05] 0.006[0.15]
51-85183-*A
0-5
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CY62157EV30 MoBL(R)
Document History Page
Document Title: CY62157EV30 MoBL(R), 8 Mbit (512K x 16) Static RAM Document Number: 38-05445 Rev. ** *A ECN No. 202940 291272 Orig. of Change AJU SYT Submission Date See ECN See ECN New Data Sheet Converted from Advance Information to Preliminary Removed 48-TSOP I Package and the associated footnote Added footnote stating 44 TSOP II Package has only one CE on Page # 2 Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed ICCDR from 4 to 4.5 A Changed tOHA from 6 to 10 ns for both 35 and 45 ns Speed Bins Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for 35 and 45 ns Speed Bins respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns Speed Bins respectively Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively Added Lead-Free Package Information Converted from Preliminary to Final. Changed ball E3 from DNU to NC Removed redundant footnote on DNU. Removed 35 ns speed bin Removed "L" bin Added 48 pin TSOP I package Added Automotive product information. Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25 mA for test condition f = fax = 1/tRC. Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz. Changed the ISB1 and ISB2 Max value from 4.5 A to 8 A and Typ value from 0.9 A to 2 A respectively. Modified ISB1 test condition to include BHE, BLE Updated Thermal Resistance table. Changed Test Load Capacitance from 50 pF to 30 pF. Added Typ value for ICCDR . Changed the ICCDR Max value from 4.5 A to 5 A Corrected tR in Data Retention Characteristics from 100 s to tRC ns. Changed tLZOE from 3 to 5 Changed tLZCE from 6 to 10 Changed tHZCE from 22 to 18 Changed tLZBE from 6 to 5 Changed tPWE from 30 to 35 Changed tSD from 22 to 25 Changed tLZWE from 6 to 10 Added footnote #15 Updated the ordering Information and replaced the Package Name column with Package Diagram. Modified Data sheet to include x8 configurability. Updated the Ordering Information table Removed Automotive-E information Added Preliminary Automotive-A information Added footnote #10 related to ISB2 and ICCDR Added footnote #15 related AC timing parameters Converted Automotive-A specs from preliminary to final Updated footnote #9 Description of Change
*B
444306
NXR
See ECN
*C *D
467052 925501
NXR VKN
See ECN See ECN
*E
1045801
VKN
See ECN
Document #: 38-05445 Rev. *F
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CY62157EV30 MoBL(R)
Document Title: CY62157EV30 MoBL(R), 8 Mbit (512K x 16) Static RAM Document Number: 38-05445 Rev. *F ECN No. 2724889 Orig. of Change NXR/AESA Submission Date 06/26/09 Description of Change Added Automotive-E information Included -45ZXA/-55ZSXE/-55ZXE parts in the Ordering Information table
Sales, Solutions, and Legal Information
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(c) Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05445 Rev. *F
Revised June 26, 2009
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MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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